Package in VHDL
PACKAGE the name itself indicates that the VHDL constructs
are written in a source file and synthesized and stored
(Packed) in a library with package name,further it can be used in other source file by declaring
name of the package along with library where it has been stored, in the
parent source file.
A package includes constant declarations, signal
declarations, type declarations, subtype declarations, signal declarations,
variable declarations, Procedure and functions etc.
Mainly there are two parts in PACKAGE
1. PACKAGE
Declaration
2. PACKAGE
Declaration Body
PACKAGE Declaration:
The PACKAGE declaration part contains declarations
that may be shared between different entity units. If provides the interface
i.e items that are visible to the other entity units.
Syntax:
PACKAGE package_name IS
Component declarations ;
Subtype declarations;
Variable declarations;
Constant declarations;
Procedure declarations;
Function declarations;
END package_name;
PACKAGE
body declaration:
syntax:
PACKAGE BODY package_name IS
Definition of procedure;
Definition of function;
END package _name;
Example: 1
4 bit RCA using fulladder as a component without package
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
entity
RCA4 is
Port ( cin : in STD_LOGIC;
x,y : in STD_LOGIC_VECTOR (3 downto 0);
sum : out
STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end
RCA4;
architecture structural of RCA4 is
component fulladd(a,b,c:in std_logic;
sum,cout:out std_logic);
end component;
signal c: std_logic_vector(3 downt0 1);
begin
x1:
fulladd port map ( x(0),y(0),cin,sum(0),c(1));
x2:
fulladd port map ( x(1),y(1),c(1),sum(1),c(2));
x3:
fulladd port map ( x(2),y(2),c(2),sum(2),c(3));
x4:
fulladd port map ( x(3),y(3),c(3)sum(3),cout);
end structural;
Definitions of fulladd:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladd is
port( a,b,c:in std_logic;
sum,ca:out std_logic);
end fulladd;
architecture dataflow of fulladd is
begin
sum<= a xor b xor c;
ca<= (a and b) or (b and c) or (a and c);
end dataflow;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladd is
port( a,b,c:in std_logic;
sum,ca:out std_logic);
end fulladd;
architecture dataflow of fulladd is
begin
sum<= a xor b xor c;
ca<= (a and b) or (b and c) or (a and c);
end dataflow;
4bit ripple carry adder using fulladder as a component. Only the component interface declaration is done in package with the name fulladd_package.
PACKAGE declaration:
Example2: 4 bit Ripple Carry Adder using package declaration
library
IEEE;
use
IEEE.STD_LOGIC_1164.all;
-----------------package
declaration------------------------
package
fulladd_package is
component
fulladd is
port(cin,x,y:in
std_logic;
s,cout:
out std_logic);
end
component;
end
fulladd_package;
----------- 4 bit Ripple Carry Adder -------------------------
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
work.fulladd_package.all; --package
name where component interfaces are
declared
entity
RCA4 is
Port ( cin : in STD_LOGIC;
x,y : in STD_LOGIC_VECTOR (3 downto 0);
sum : out
STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end
RCA4;
architecture structural of RCA4 is
signal
c:std_logic_vector( 3 downto 1);
begin
x1: fulladd port map ( x(0),y(0),cin,sum(0),c(1));
x2: fulladd port map (x(1),y(1),c(1),sum(1),c(2));
x3: fulladd port map ( x(2),y(2),c(2),sum(2),c(3));
x4: fulladd port map ( x(3),y(3),c(3),sum(3),cout);
end structural;
Here even though component is declared in package but the relation between input and output (operation ) is not defined hence their is a necessity of writing the component definition in another file ie. definition of fulladd for sum and carry expression.( fulladd definition given above).
