Thursday 20 March 2014

VHDL CODE FOR D-FLIPFLOP USING WAIT STATEMENTS



-------------4 BIT COUNTER USING WAIT STATEMENT-----------------
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity counter is
    Port ( clk : in  STD_LOGIC;
           q : inout  STD_LOGIC_VECTOR (3 downto 0):=(others=>'0'));
end counter;
architecture Behavioral of counter is
begin
process
begin
wait until (clk'event and clk ='1');
q<=q+1;
end process;
end Behavioral;

VHDL code for D flip flop with synchronous reset using 'WAIT UNTIL' statement
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DFF_wait_SYNCH is
    Port ( clk,reset,d : in  STD_LOGIC;
                    q : inout  STD_LOGIC;
                       qb:out std_logic);
end DFF_wait_SYNCH;

architecture Behavioral of DFF_wait_SYNCH is

begin
process
begin
wait until (clk'event and clk='1');
if reset='1' then
q<=q;
else
q<=d;
qb<=not q;
end if;
end process;
end Behavioral;

                             
VHDL code for D flip flop with Asynchronous reset using 'WAIT UNTIL' statement
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DFF_wait_ASYNCH is
    Port ( clk,reset,d : in  STD_LOGIC;
                               q : inout  STD_LOGIC;
                                      qb:out std_logic);
end DFF_wait_ASYNCH;

architecture Behavioral of DFF_wait_ASYNCH is

begin
process
begin
if reset='1' then
q<=q;
ELSE
wait until (clk'event and clk='1');
q<=d;
end if;
qb<=not q;
end process;
end Behavioral;

VHDL code for D flip flop with synchronous reset using 'WAIT ON' statement

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DFF_waitON_SYNCH is
    Port ( clk,reset,d : in  STD_LOGIC;
                               q : inout  STD_LOGIC;
                                      qb:out std_logic);
end DFF_waitON_SYNCH;

architecture Behavioral of DFF_waitON_SYNCH is

begin
process
begin
wait ON clk;
IF RISING_EDGE(CLK) THEN
if reset='1' then
q<=q;
else
q<=d;
end if;
qb<=not q;
END IF;
end process;
end Behavioral;


VHDL code for D flip flop with Asynchronous reset using 'WAIT ON' statement

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DFF_waitON_ASYNCH is
    Port ( clk,reset,d : in  STD_LOGIC;
                               q : inout  STD_LOGIC:='0';
                                      qb:out std_logic);
end DFF_waitON_ASYNCH;
                                
architecture Behavioral of DFF_waitON_ASYNCH is
begin

process
begin
if reset='1' then
q<=q;
else
IF RISING_EDGE(CLK) THEN
q<=d;
end if;
END IF;
wait ON clk;
qb<=not q;
end process;
end Behavioral;

            D-FlipFlop using Synchronous SET and RESET

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SYNCH_SET_RESET is
    Port ( CLK,SET,RESET,Din : in  STD_LOGIC;
           Q : inout  STD_LOGIC;
           Qb : out  STD_LOGIC);
end SYNCH_SET_RESET;

architecture Behavioral of SYNCH_SET_RESET is

begin
process(clk,din,reset,set)
begin
if reset='1' then
q<='0';
elsif set='1' then
q<='1';
elsif rising_edge(clk) then
q<=din;
else
q<=q;
end if;
qb<=not q;
end process;

end Behavioral;
 

            D-FlipFlop using Asynchronous SET and RESET
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ASYNCH_SET_RESET is
    Port ( CLK,SET,RESET,Din : in  STD_LOGIC;
           Q : inout  STD_LOGIC;
           Qb : out  STD_LOGIC);
end ASYNCH_SET_RESET;

architecture Behavioral of ASYNCH_SET_RESET is

begin
process(clk,din,reset,set)
begin
if rising_edge(clk) then
if reset='1' then
q<='0';
elsif set='1' then
q<='1';
else
q<=din;
end if;

end if;
qb<=not q;
end process;

end Behavioral;
Posted by at 2 comments:

VHDL CODE FOR CONVERTERS



----------------------------4 BIT BINARY TO GRAY CONVERTER--------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BintoGray is
    Port ( B : in  STD_LOGIC_VECTOR(3 DOWNTO 0);
           G : out  STD_LOGIC_VECTOR(3 DOWNTO 0));
end BintoGray;
architecture Behavioral of BintoGray is
begin
G(3)<=B(3);
G(2)<= B(2) XOR B(3);
G(1)<= B(1) XOR B(2);
G(0)<= B(0) XOR B(1);
end Behavioral;
--------------------------------N BIT BINARY TO GRAY CONVERTER-------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity NbitBin_Gray is
generic(constant n:integer:=6);
    Port ( B : in  STD_LOGIC_VECTOR (n-1 downto 0);
           G : out  STD_LOGIC_VECTOR (n-1 downto 0));
end NbitBin_Gray;

architecture Behavioral of NbitBin_Gray is

begin
process(b)
begin
for i in integer range  0 to n-2 loop
g(n-1)<=b(n-1);
g(i)<=b(i) XOR b(i+1);
end loop;
end process;
end Behavioral;
Posted by at No comments:

Wednesday 12 March 2014

VHDL Code for Synchronous and Asyncronous counter



---------------SYNCHRONOUS DOWN COUNTER USING SIGNAL----------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity Synch_down is
    Port ( clk,rst : in  STD_LOGIC;
                 
           q : out  STD_LOGIC_VECTOR (3 downto 0));
end Synch_down;

architecture Behavioral of Synch_down is
signal count: std_logic_vector(3 downto 0):=(others=>'1');

begin
process(clk)
begin
if rising_edge(clk) then
if rst='0' then              ------rst is synchronised with  clk
count<= count-1;
else
count<="1111";
 end if;
q<= count;
end if;
end process;
end Behavioral;

-------------SYNCHRONOUS DOWN COUNTER WITHOUT USING SIGNAL AND VARIABLE----------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity Synch_down is
    Port ( clk,rst : in  STD_LOGIC;
                 
           q : inout  STD_LOGIC_VECTOR (3 downto 0));
end Synch_down;

architecture Behavioral of Synch_down is

begin
process(clk)
begin
if rising_edge(clk) then
if rst='0' then              ------rst is synchronised with  clk
q<=q-1;
else
q<="1111";
end if;
end if;
end process;
end Behavioral;

-------------------------------SYNCHRONOUS UP COUNTER USING SIGNAL  ---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity Synch_up is
    Port ( clk,rst : in  STD_LOGIC;
                 
           q : out  STD_LOGIC_VECTOR (3 downto 0));
end Synch_up;

architecture Behavioral of Synch_up is
signal count: std_logic_vector(3 downto 0):=(others=>'0');

begin
process(clk)
begin
if rising_edge(clk) then
if rst='0' then              ------rst is synchronised with  clk
count<= count+1;
end if;
else
count<="0000";
 end if;
q<= count;

end process;
end Behavioral;

-------------ASYNCHRONOUS DOWN COUNTER WITHOUT USING SIGNAL AND VARIABLE-----------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity aSynch_down is
    Port ( clk,rst : in  STD_LOGIC;
                q : inout  STD_LOGIC_VECTOR (3 downto 0):=(others=>'1'));
end aSynch_down;

architecture Behavioral of aSynch_down is


begin
process(clk)

begin
if rst='1' then     ----rst is not synchronised with  clk
 if rising_edge(clk) then           
q<= q-1;
end if;
else
q<="0000";
end if;
end process;
end Behavioral;

---------------ASYNCHRONOUS UP COUNTER  WITHOUT USING SIGNAL AND VARIABLE-------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity aSynch_up is
    Port ( clk,rst : in  STD_LOGIC;
                q : inout  STD_LOGIC_VECTOR (3 downto 0):=(others=>'0'));
end aSynch_up;

architecture Behavioral of aSynch_up is


begin
process(clk)

begin
if rst='1' then     ----rst is not synchronised with  clk
 if rising_edge(clk) then           
q<= q+1;
end if;
else
q<="0000";
end if;
end process;
end Behavioral;

----------ASYNCHRONOUS UP COUNTER USING SIGNAL---------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity aSynch_up is
    Port ( clk,rst : in  STD_LOGIC;
                 
           q : out  STD_LOGIC_VECTOR (3 downto 0));
end aSynch_up;

architecture Behavioral of aSynch_up is

begin
process(clk)
variable count: std_logic_vector(3 downto 0):=(others=>'0');
begin
if rst='0' then ------rst is not synchronised with  clk
if rising_edge(clk) then           
count:= count+1;
end if;
else
count:="0000";
end if;
q<= count;
end process;
end Behavioral;

----------4 BIT EVEN COUNTER  USING SIGNAL---------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity EVEN_COUNTER is
    Port ( clk, : in  STD_LOGIC;
                 
           q : out  STD_LOGIC_VECTOR (3 downto 0));
end EVEN_COUNTER;

architecture Behavioral of EVEN_COUNTER is


begin
process(clk)
variable count: std_logic_vector(3 downto 0):=(others=>'0');
begin
if rising_edge(clk) then            
count:= count+2;
end if;
q<= count;
end process;
end Behavioral;

---------- N BIT EVEN COUNTER  USING SIGNAL---------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity NbitEVEN_COUNTER is
generic (constant n:integer:=4);
    Port ( clk : in  STD_LOGIC;
                 
           q : out  STD_LOGIC_VECTOR (n-1 downto 0));
end NbitEVEN_COUNTER;

architecture Behavioral of NbitEVEN_COUNTER is
begin
process(clk)
variable count: std_logic_vector(n-1 downto 0):=(others=>'0');
begin
if rising_edge(clk) then           
count:= count+2;
end if;
q<= count;
end process;
end Behavioral;
Posted by at No comments:
Subscribe to: Posts (Atom)