Package body Declaration in VHDL

VHDL PACKAGE BODY Declaration

Functions and Procedure  definitions must be written in the package body declaration.

1.  VHDL Functions
A function executes a sequential algorithm and returns a single value to the calling program. We can think of a function as a generalization of expressions. 

 Syntax:

 function identifier [(parameter_interface_list)]
return value is
{subprogram declarations}
begin
{sequential statements}
end [function] [identifier];


Only parameters of  mode 'in' are allowed in function calls and are treated as 'constant' by default.  in parameter list output signals must be declared by starting with the keyword signal.

Example : 4 bit Ripple Carry Adder using functions in  Package

library IEEE;
use IEEE.STD_LOGIC_1164.all;
-------------------------------------------------package declaration-----------------------------
package fa_funct is
subtype bit2 is std_logic_vector(1 downto 0);
function fadd( a,b,c: in std_logic) return bit2;
--signal z: std_logic_vector(1 downto 0);
end fa_funct;
------------------------------------------------package body declaration------------------------
package body fa_funct is

function fadd( a,b,c: in std_logic) return bit2 is
begin
return  (a xor b xor c) &((a and b) or (b and c) or (a and c));
end fadd;
 end fa_funct; 



4 bit RCA  using function as package


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.fa_funct.all;

entity RCA_funct_PACK is

    Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
           sum : out  STD_LOGIC_VECTOR (3 downto 0);
           zin : in  STD_LOGIC;
           cout : out  STD_LOGIC);
end RCA_funct_PACK;

architecture Behavioral of RCA_funct_PACK is
signal s1,s2,s3,s4:std_logic_vector( 1 downto 0);

begin

s1<= fadd(a(0),b(0),zin);
s2<=fadd(a(1),b(1),s1(0));
s3<= fadd(a(2),b(2),s2(0));
s4<= fadd(a(3),b(3),s3(0));
sum <=s4(1) & s3(1)& s2(1) & s1(1);
cout<= s4(0);
end Behavioral;




4 bit RCA Using Procedure:
 fulladder is defined by using procedure and stored in package
 

library IEEE;
use IEEE.STD_LOGIC_1164.all;

-------------------------------package declaration---------------------------------

package fa_pack is

procedure fa (a,b,c    : in std_logic;
signal s,carr: out std_logic);
end fa_pack;

package body fa_pack is

-------------------------------package body declaration---------------

 procedure fa (a,b,c    : in std_logic;
 signal s,carr: out std_logic) is

--------------------------------------procedure body ------------------------

 begin
 s <= a xor b xor c;
 carr <= (a and b) or (b and c) or (a and b);
 end fa;
 --------end of proceduer body-------------------------
end fa_pack;
------------end of package body------------------------  

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.fa_pack.all;

entity RCA_PACK is
    Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
           sum : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC;
           cin : in  STD_LOGIC);
end RCA_PACK;

architecture Behavioral of RCA_PACK is
signal ca:std_logic_vector(3 downto 1);
begin
x0:fa(a(0),b(0),cin,sum(0),ca(1));
x1: fa(a(1),b(1),ca(1),sum(1),ca(2));
x2: fa(a(2),b(2),ca(2),sum(2),ca(3));
x3: fa(a(3),b(3),ca(3),sum(3),cout);
end Behaviora

N Bit RCA using procedure with same full adder  package as mentioned above


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.fa_pack.all;

entity RCA_PACK is
generic (constant n:integer:= 4);
    Port ( a,b : in  STD_LOGIC_VECTOR (n-1 downto 0);
           sum : out  STD_LOGIC_VECTOR (n-1 downto 0);
           cout : out  STD_LOGIC;
           cin : in  STD_LOGIC);
end RCA_PACK;

architecture Behavioral of RCA_PACK is
signal ca:std_logic_vector(n downto 0);
begin
ca(0)<= cin;
FA_Nbit:for i in 0 to n-1 generate
begin

FA_ADD:fa(a(i),b(i),ca(i),sum(i),ca(i+1));

end generate;
cout<= ca(n);
end Behavioral;