VHDL CODE FOR D-FLIPFLOP USING WAIT STATEMENTS

-------------4 BIT COUNTER USING WAIT STATEMENT-----------------

library ieee;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity counter is

    Port ( clk : in  STD_LOGIC;

           q : inout  STD_LOGIC_VECTOR (3 downto 0):=(others=>'0'));

end counter;

architecture Behavioral of counter is

begin

process

begin

wait until (clk'event and clk ='1');

q<=q+1;

end process;

end Behavioral;

VHDL code for D flip flop with synchronous reset using 'WAIT UNTIL' statement

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity DFF_wait_SYNCH is

    Port ( clk,reset,d : in  STD_LOGIC;

                    q : inout  STD_LOGIC;

                       qb:out std_logic);

end DFF_wait_SYNCH;

architecture Behavioral of DFF_wait_SYNCH is

begin

process

begin

wait until (clk'event and clk='1');

if reset='1' then

q<=q;

else

q<=d;

qb<=not q;

end if;

end process;

end Behavioral;

                             

VHDL code for D flip flop with Asynchronous reset using 'WAIT UNTIL' statement

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity DFF_wait_ASYNCH is

    Port ( clk,reset,d : in  STD_LOGIC;

                               q : inout  STD_LOGIC;

                                      qb:out std_logic);

end DFF_wait_ASYNCH;

architecture Behavioral of DFF_wait_ASYNCH is

begin

process

begin

if reset='1' then

q<=q;

ELSE

wait until (clk'event and clk='1');

q<=d;

end if;

qb<=not q;

end process;

end Behavioral;

VHDL code for D flip flop with synchronous reset using 'WAIT ON' statement

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity DFF_waitON_SYNCH is

    Port ( clk,reset,d : in  STD_LOGIC;

                               q : inout  STD_LOGIC;

                                      qb:out std_logic);

end DFF_waitON_SYNCH;

architecture Behavioral of DFF_waitON_SYNCH is

begin

process

begin

wait ON clk;

IF RISING_EDGE(CLK) THEN

if reset='1' then

q<=q;

else

q<=d;

end if;

qb<=not q;

END IF;

end process;

end Behavioral;

VHDL code for D flip flop with Asynchronous reset using 'WAIT ON' statement

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity DFF_waitON_ASYNCH is

    Port ( clk,reset,d : in  STD_LOGIC;

                               q : inout  STD_LOGIC:='0';

                                      qb:out std_logic);

end DFF_waitON_ASYNCH;

                                

architecture Behavioral of DFF_waitON_ASYNCH is

begin

process

begin

if reset='1' then

q<=q;

else

IF RISING_EDGE(CLK) THEN

q<=d;

end if;

END IF;

wait ON clk;

qb<=not q;

end process;

end Behavioral;

            D-FlipFlop using Synchronous SET and RESET

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SYNCH_SET_RESET is
    Port ( CLK,SET,RESET,Din : in  STD_LOGIC;
           Q : inout  STD_LOGIC;
           Qb : out  STD_LOGIC);
end SYNCH_SET_RESET;

architecture Behavioral of SYNCH_SET_RESET is

begin
process(clk,din,reset,set)
begin
if reset='1' then
q<='0';
elsif set='1' then
q<='1';
elsif rising_edge(clk) then
q<=din;
else
q<=q;
end if;
qb<=not q;
end process;

end Behavioral;
 

            D-FlipFlop using Asynchronous SET and RESET
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ASYNCH_SET_RESET is
    Port ( CLK,SET,RESET,Din : in  STD_LOGIC;
           Q : inout  STD_LOGIC;
           Qb : out  STD_LOGIC);
end ASYNCH_SET_RESET;

architecture Behavioral of ASYNCH_SET_RESET is

begin
process(clk,din,reset,set)
begin
if rising_edge(clk) then
if reset='1' then
q<='0';
elsif set='1' then
q<='1';
else
q<=din;
end if;

end if;
qb<=not q;
end process;

end Behavioral;