VHDL Code for Synchronous and Asyncronous counter

---------------SYNCHRONOUS DOWN COUNTER USING SIGNAL----------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity Synch_down is

    Port ( clk,rst : in  STD_LOGIC;

                 

           q : out  STD_LOGIC_VECTOR (3 downto 0));

end Synch_down;

architecture Behavioral of Synch_down is

signal count: std_logic_vector(3 downto 0):=(others=>'1');

begin

process(clk)

begin

if rising_edge(clk) then

if rst='0' then              ------rst is synchronised with  clk

count<= count-1;

else

count<="1111";

 end if;

q<= count;

end if;

end process;

end Behavioral;

-------------SYNCHRONOUS DOWN COUNTER WITHOUT USING SIGNAL AND VARIABLE----------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity Synch_down is

    Port ( clk,rst : in  STD_LOGIC;

                 

           q : inout  STD_LOGIC_VECTOR (3 downto 0));

end Synch_down;

architecture Behavioral of Synch_down is

begin

process(clk)

begin

if rising_edge(clk) then

if rst='0' then              ------rst is synchronised with  clk

q<=q-1;

else

q<="1111";

end if;

end if;

end process;

end Behavioral;

-------------------------------SYNCHRONOUS UP COUNTER USING SIGNAL  ---------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity Synch_up is

    Port ( clk,rst : in  STD_LOGIC;

                 

           q : out  STD_LOGIC_VECTOR (3 downto 0));

end Synch_up;

architecture Behavioral of Synch_up is

signal count: std_logic_vector(3 downto 0):=(others=>'0');

begin

process(clk)

begin

if rising_edge(clk) then

if rst='0' then              ------rst is synchronised with  clk

count<= count+1;

end if;

else

count<="0000";

 end if;

q<= count;

end process;

end Behavioral;

-------------ASYNCHRONOUS DOWN COUNTER WITHOUT USING SIGNAL AND VARIABLE-----------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity aSynch_down is

    Port ( clk,rst : in  STD_LOGIC;

                q : inout  STD_LOGIC_VECTOR (3 downto 0):=(others=>'1'));

end aSynch_down;

architecture Behavioral of aSynch_down is

begin

process(clk)

begin

if rst='1' then     ----rst is not synchronised with  clk

 if rising_edge(clk) then           

q<= q-1;

end if;

else

q<="0000";

end if;

end process;

end Behavioral;

---------------ASYNCHRONOUS UP COUNTER  WITHOUT USING SIGNAL AND VARIABLE-------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity aSynch_up is

    Port ( clk,rst : in  STD_LOGIC;

                q : inout  STD_LOGIC_VECTOR (3 downto 0):=(others=>'0'));

end aSynch_up;

architecture Behavioral of aSynch_up is

begin

process(clk)

begin

if rst='1' then     ----rst is not synchronised with  clk

 if rising_edge(clk) then           

q<= q+1;

end if;

else

q<="0000";

end if;

end process;

end Behavioral;

----------ASYNCHRONOUS UP COUNTER USING SIGNAL---------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity aSynch_up is

    Port ( clk,rst : in  STD_LOGIC;

                 

           q : out  STD_LOGIC_VECTOR (3 downto 0));

end aSynch_up;

architecture Behavioral of aSynch_up is

begin

process(clk)

variable count: std_logic_vector(3 downto 0):=(others=>'0');

begin

if rst='0' then ------rst is not synchronised with  clk

if rising_edge(clk) then           

count:= count+1;

end if;

else

count:="0000";

end if;

q<= count;

end process;

end Behavioral;

----------4 BIT EVEN COUNTER  USING SIGNAL---------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity EVEN_COUNTER is

    Port ( clk, : in  STD_LOGIC;

                 

           q : out  STD_LOGIC_VECTOR (3 downto 0));

end EVEN_COUNTER;

architecture Behavioral of EVEN_COUNTER is

begin

process(clk)

variable count: std_logic_vector(3 downto 0):=(others=>'0');

begin

if rising_edge(clk) then            

count:= count+2;

end if;

q<= count;

end process;

end Behavioral;

---------- N BIT EVEN COUNTER  USING SIGNAL---------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

use IEEE.STD_LOGIC_unsigned.ALL;

entity NbitEVEN_COUNTER is

generic (constant n:integer:=4);

    Port ( clk : in  STD_LOGIC;

                 

           q : out  STD_LOGIC_VECTOR (n-1 downto 0));

end NbitEVEN_COUNTER;

architecture Behavioral of NbitEVEN_COUNTER is

begin

process(clk)

variable count: std_logic_vector(n-1 downto 0):=(others=>'0');

begin

if rising_edge(clk) then           

count:= count+2;

end if;

q<= count;

end process;

end Behavioral;